The present invention relates to semiconductor devices, and more specifically, to finFET-type semiconductor devices.
Studies have shown that silicon germanium (SiGe) material allows for greater hole mobility compared to pure silicon material. Therefore, recent trends in finFET technology have led to semiconductor devices that utilize silicon germanium (SiGe) fins as opposed to silicon (Si) for p-type transistors.
Referring to FIGS. 1A-1D, a conventional fabrication method for forming a finFET semiconductor device 100 including a SiGe fin 102 is illustrated. In general, a SiGe fin 102 is initially formed on a surface of a semiconductor substrate 104 as illustrated in FIG. 1A. This may be done, for example, by epitaxial growth of a SiGe layer on a silicon substrate, wherein the SiGe layer becomes compressively strained as a result of the lattice matching of Ge atoms to Si atoms in the substrate 104. The SiGe layer is patterned as known in the art to form the compressively strained SiGe fin 102. Referring to FIG. 1B, a sacrificial gate layer 106 (i.e., dummy gate layer) is deposited on the substrate 104, which covers the SiGe fin 102. Turning to FIG. 1C, the sacrificial gate layer 106 is patterned to form a dummy gate element 107. The etching process used to pattern form the dummy gate element 107 also recesses the height of the SiGe fin 102 (i.e., pulls down the SiGe fin) as further illustrated in FIG. 1C. Referring to FIG. 1D, a block spacer layer 108 is deposited on the substrate 104 and covers the previous etched portions of the SiGe fin 102 and the upper surface of the dummy gate element 107. Referring to FIG. 1E, the block spacer layer 108 is anisotropically etched to form gate spacers 110 that define a gate stack 112 wrapping around the SiGe fin 102. However, etching process used to form the gate spacers also etches the underlying SiGe fin 102 and further reduces the fin height as illustrated in FIG. 1E. The resulting SiGe fin 120 is therefore has dual cut-outs on opposing sides of the dummy gate element 107 and spacers 108. That is, a first stepped portion 114 of the SiGe fin 102 is formed beneath dummy gate element 107, while a second stepped portion 116 of the SiGe fin 102 is formed below the first stepped portion 114 as illustrated in FIG. 1F. Consequently, when forming the gate stack 112 according to conventional fabrication methods, the underlying SiGe fin 102 is also etched which partially relaxes the compressive strain, i.e., reduces the strain, in the source/drain region as illustrated in FIG. 1G. The loss in strain can be as much as approximately 50% of the original strain created when forming the initial semiconductor fin. The strain relaxation typically increases as the fin extends from the gate spacers toward the opposing end of the fin 102. Therefore, the strain relaxation degrades overall device performance.